liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Sun, 1 Mar 2015 15:45:50 +0000 (16:45 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Sun, 1 Mar 2015 15:48:41 +0000 (16:48 +0100)
commit649cdeb2655e48daff9f2b69ffb0b3bfc6db0835
treed7f546137bb76dbae18405c5e3732c68882bf813
parentbd4d3cd73ba9d4033092d3bb77c42f1d75c2f8bf
liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen
misoclib/com/liteeth/common.py
misoclib/com/liteeth/example_designs/targets/base.py
misoclib/com/liteeth/generic/__init__.py
misoclib/mem/litesata/common.py
misoclib/mem/litesata/example_designs/targets/bist.py
misoclib/mem/litesata/frontend/bist.py
misoclib/tools/litescope/bridge/uart2wb.py
misoclib/tools/litescope/common.py
misoclib/tools/litescope/core/storage.py
misoclib/tools/litescope/example_designs/targets/simple.py