Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
authorStaf Verhaegen <staf@fibraservi.eu>
Fri, 8 May 2020 17:23:35 +0000 (19:23 +0200)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Fri, 8 May 2020 17:23:44 +0000 (18:23 +0100)
commit65a21c71b9524844076238c64944700c66ac816e
tree54507237ae6a11e05fee289a207c051c25b28b22
parentd074b9dc32da2880fcb79f6d20e9a7e89c189066
Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
a9/326bb2f501c2c5fe95c85207a2f95091cadd09 [new file with mode: 0644]