power: Add basic DVFS support for gem5
authorStephan Diestelhorst <stephan.diestelhorst@arm.com>
Mon, 30 Jun 2014 17:56:06 +0000 (13:56 -0400)
committerStephan Diestelhorst <stephan.diestelhorst@arm.com>
Mon, 30 Jun 2014 17:56:06 +0000 (13:56 -0400)
commit65cea4708e2f2f2cb361e12b6385d4bc29618223
tree9f190702d43e89e2ddb44b6af363330f301ec8fb
parent641e6028304187468b94753752555e9d082a77ac
power: Add basic DVFS support for gem5

Adds DVFS capabilities to gem5, by allowing users to specify lists for
frequencies and voltages in SrcClockDomains and VoltageDomains respectively.
A separate component, DVFSHandler, provides a small interface to change
operating points of the associated domains.

Clock domains will be linked to voltage domains and thus allow separate clock,
but shared voltage lines.

Currently all the valid performance-level updates are performed with a fixed
transition latency as specified for the domain.

Config file example:
...
vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V'])
tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster1.clk_domain.domain_id = 0
tsys.cluster2.clk_domain.domain_id = 1
tsys.cluster1.clk_domain.voltage_domain = vd
tsys.cluster2.clk_domain.voltage_domain = vd
tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain,
                             tsys.cluster2.clk_domain]
tsys.dvfs_handler.enable = True
14 files changed:
src/arch/alpha/AlphaSystem.py
src/arch/mips/MipsSystem.py
src/sim/ClockDomain.py
src/sim/DVFSHandler.py [new file with mode: 0644]
src/sim/SConscript
src/sim/System.py
src/sim/VoltageDomain.py
src/sim/clock_domain.cc
src/sim/clock_domain.hh
src/sim/dvfs_handler.cc [new file with mode: 0644]
src/sim/dvfs_handler.hh [new file with mode: 0644]
src/sim/eventq.hh
src/sim/voltage_domain.cc
src/sim/voltage_domain.hh