git.libre-soc.org Git - riscv-isa-sim.git/commit

author	Luke Kenneth Casson Leighton <lkcl@lkcl.net>
	Sun, 30 Sep 2018 04:13:50 +0000 (05:13 +0100)
committer	Luke Kenneth Casson Leighton <lkcl@lkcl.net>
	Sun, 30 Sep 2018 04:13:50 +0000 (05:13 +0100)
commit	6613cfeb94dbfa8a43c17594829c12d4aca0aad4
tree	f1459d96e372e12bffba8f30dadc6849b2de9032	tree
parent	8bdeded4ebf4081017b44789067172fd2d3a784c	commit \| diff

use an alternative logic for detecting scalar / loop-end

instead of pre-checking do the check for "all-scalar" during the
first loop iteration i.e. when registers are first accessed

riscv/insn_template_sv.cc		diff \| blob \| history
riscv/sv.cc		diff \| blob \| history
riscv/sv_decode.h		diff \| blob \| history

Simple-V augmented version of spike

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