add larger PLL reset countdown to give ULX3S a chance to stabilise
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 12 Feb 2022 15:54:33 +0000 (15:54 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 12 Feb 2022 15:54:33 +0000 (15:54 +0000)
commit6639ab0c1689a429d503b94b3c656ae58ad54d95
tree65b5c9857a3122eab2ecdaeaf7d6459a64f8e10f
parent50833dc849ac9da022c731b5244e85ddd087eefa
add larger PLL reset countdown to give ULX3S a chance to stabilise
fpga/top-generic.vhdl