uart: new design using FHDL and bank (TX only, incomplete)
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Sat, 17 Dec 2011 23:29:37 +0000 (00:29 +0100)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Sat, 17 Dec 2011 23:29:37 +0000 (00:29 +0100)
commit6664af73d11166b97be77470e9ff76d57dd90452
treee09820df577104de7f142a7181fa0318888d2d7c
parentbb21f7584a34fb8044735a0da697c30d70ee6297
uart: new design using FHDL and bank (TX only, incomplete)
build.py
milkymist/uart/__init__.py
top.py
verilog/uart/uart.v [deleted file]
verilog/uart/uart_transceiver.v [deleted file]