Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 8 May 2020 16:55:52 +0000 (17:55 +0100)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Fri, 8 May 2020 16:56:26 +0000 (17:56 +0100)
commit666b5ec236415474bce36171e572ffb094568ecd
tree9fa88fe39e20a9a38b416207f54c483c4ef9e492
parentdddc7bbedf9705098b28dc32781ed95badd94acf
Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
72/a389c143c39fdc140f31087b0dec74561d33d4 [new file with mode: 0644]