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intel: Enable CCS_E for R24_UNORM_X8_TYPELESS on TGL+
authorNanley Chery <nanley.g.chery@intel.com>
Thu, 8 Aug 2019 20:40:08 +0000 (13:40 -0700)
committerNanley Chery <nanley.g.chery@intel.com>
Mon, 28 Oct 2019 17:47:05 +0000 (10:47 -0700)
commit6670e07a6efb69951c45583b51d51de31c9e7119
tree111b955273d57ecce57ec658d1498c05bfaa0ab9tree
parentf93bc14618ae22a3d3b8030be6ba58d589f0bab8commit | diff
intel: Enable CCS_E for R24_UNORM_X8_TYPELESS on TGL+

While this format isn't listed in BSpec: 53911, other documentation and
empirical evidence suggest that it's fine to remap it to R32_FLOAT. I've
filed a bug for the BSpec page.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
src/intel/common/gen_aux_map.c diff | blob | history
src/intel/isl/isl_format.c diff | blob | history