projects / nmigen.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 05bfabf) | patch
back.rtlil: infer bit width for instance parameters.
authorwhitequark <cz@m-labs.hk>
Wed, 27 Nov 2019 17:58:42 +0000 (17:58 +0000)
committerwhitequark <cz@m-labs.hk>
Wed, 27 Nov 2019 17:58:42 +0000 (17:58 +0000)
commit668c2125280b75102e4a21220eff768c5b37f0d7
tree24102d3349eb30d87eb66383183ec313492a55d1tree
parent05bfabff87c0a823e49af574921bd906b2f4edf4commit | diff
back.rtlil: infer bit width for instance parameters.

Otherwise, Yosys assumes it is always 32, which is often
inappropriate.
nmigen/back/rtlil.py diff | blob | history