Re: [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 13 May 2020 19:54:06 +0000 (20:54 +0100)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Wed, 13 May 2020 19:54:30 +0000 (20:54 +0100)
commit66b1205086ce67673ca8d2b5c4ba0bbf75f05085
tree28ee96f1fa6fa6f39ea28474b09da1609b99cdbe
parent6c18a4277a6283dfa6f0243b918d362c43468d56
Re: [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
1e/23846cfcf48a20e8be52eee95a6616ff3d500d [new file with mode: 0644]