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(parent: 886680a) | patch
vc707 axi enhancements (#24)
authorWesley W. Terpstra <wesley@sifive.com>
Fri, 30 Jun 2017 19:36:33 +0000 (12:36 -0700)
committerGitHub <noreply@github.com>
Fri, 30 Jun 2017 19:36:33 +0000 (12:36 -0700)
commit66b2fd11bd1ec6a8a05c4929893c51c7570284fd
tree32d1d40f8394e8120b106b9bbed210042d1cd05btree
parent886680af49a0b7e3e5acac2678d9c5a8da9b4a5fcommit | diff
vc707 axi enhancements (#24)

1 - Print AXI-ID mappings
2 - Use half as many Deinterleaver buffers for the L2 backside
3 - Limit the Q depth on the PCIe control port to 2 (was 1584!)
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala diff | blob | history
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala diff | blob | history
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