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(parent: d7b00c8) | patch
boards/targets/arty: generate 25MHz ethernet clock with S7PLL
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Tue, 28 May 2019 07:55:06 +0000 (09:55 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Tue, 28 May 2019 07:55:06 +0000 (09:55 +0200)
commit675f78304ef613b28d4cd4c83ce87f941436ad70
treea2683ad177462106318ab11bf2962b6e47a425b2tree
parentd7b00c8c4de65834694179f15ca175f818b029bdcommit | diff
boards/targets/arty: generate 25MHz ethernet clock with S7PLL

Allow ethernet to work when sys_clk_freq != 100MHz
litex/boards/targets/arty.py diff | blob | history