Merge pull request #1036 from YosysHQ/eddie/xilinx_dram
authorEddie Hung <eddie@fpgeh.com>
Thu, 23 May 2019 20:13:10 +0000 (13:13 -0700)
committerGitHub <noreply@github.com>
Thu, 23 May 2019 20:13:10 +0000 (13:13 -0700)
commit67a4850e3505e97bcb01fb02a688beee89af6e76
treeabca4263ba6df2c3d7d749ee4d566fb56c374263
parentca4694735455512162da1d4a24429ecf350a8abe
parent99a3fee8f4a0f89f865ccf5292d5e70d59febd9f
Merge pull request #1036 from YosysHQ/eddie/xilinx_dram

Add "min bits" and "min wports" to xilinx dram rules