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(parent: 5761737) | patch
fhdl.ir: record port direction explicitly.
authorwhitequark <cz@m-labs.hk>
Thu, 13 Dec 2018 13:12:31 +0000 (13:12 +0000)
committerwhitequark <cz@m-labs.hk>
Thu, 13 Dec 2018 13:12:31 +0000 (13:12 +0000)
commit68276a0d3ffb69b5aefe2bd088a905d004fed121
treed1cae60d6209de40bb886ecf2a6031fcf8f0e8d5tree
parent576173746966e49af26b01e2cbc0c5959851b602commit | diff
fhdl.ir: record port direction explicitly.

No point in recalculating this in the backend when writing RTLIL or
Verilog port directions.
nmigen/back/rtlil.py diff | blob | history
nmigen/fhdl/ast.py diff | blob | history
nmigen/fhdl/ir.py diff | blob | history
nmigen/test/test_fhdl_ir.py diff | blob | history