add riscv-sifive-elf triple
authorPaul Sajna <sajattack@gmail.com>
Sun, 1 Mar 2020 09:39:03 +0000 (01:39 -0800)
committerPaul Sajna <sajattack@gmail.com>
Sun, 1 Mar 2020 09:39:03 +0000 (01:39 -0800)
commit68c013d13fc2c77ab7c64a0269caa5d7004667fb
treefe36a6b62972a8a391f36582566488c2f34a292b
parent54fb3a61cd5c577b77d5fa1375fb2df0fb629e76
add riscv-sifive-elf triple
litex/soc/cores/cpu/blackparrot/core.py
litex/soc/cores/cpu/minerva/core.py
litex/soc/cores/cpu/picorv32/core.py
litex/soc/cores/cpu/rocket/core.py
litex/soc/cores/cpu/vexriscv/core.py