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(parent: 9397d05) | patch
add in predication to sv instruction execution
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 30 Sep 2018 06:07:43 +0000 (07:07 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 30 Sep 2018 06:07:43 +0000 (07:07 +0100)
commit68f9627a24b22c06673cce110df43b2744adaa29
treed518fff585d3f139ab75a22d20128df2aa8075a8tree
parent9397d0502122eaf943b58d62d26d5f57c38716cdcommit | diff
add in predication to sv instruction execution

this relies on setting the value of the destination register
(and source registers) to zero.  a bad hack but it will do
riscv/insn_template_sv.cc diff | blob | history
riscv/sv.cc diff | blob | history
riscv/sv_decode.h diff | blob | history
Simple-V augmented version of spike