"fix" fdmadd DCT mul-add-sub unit test with values that will
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 23 Jul 2021 13:48:53 +0000 (14:48 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 23 Jul 2021 13:48:53 +0000 (14:48 +0100)
commit695c394aac82fa7f651ebcd7489acc419edfdb33
treefbd417d41c86f5427e66acffdc8bfebd002e0aa4
parentc7584c58ffd85d7daf5990ec9deacfe616ba81bb
"fix" fdmadd DCT mul-add-sub unit test with values that will
not cause rounding.  "good enough" for now
openpower/isa/svfparith.mdwn
src/openpower/decoder/isa/caller.py
src/openpower/decoder/isa/test_caller_svp64_dct.py