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(parent: a1120e4) | patch
ld/st mismatch in power_insn.py and sv_analysis.py
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 15 May 2023 15:37:26 +0000 (16:37 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 15 May 2023 15:37:26 +0000 (16:37 +0100)
commit6985cb406e6821cffc71143dea97991ea6dd1da2
tree18713e39433b0faa7b6c636e3c4e3574c4631e72tree
parenta1120e4dded30443bb58ed011d476a8d56cdadd7commit | diff
ld/st mismatch in power_insn.py and sv_analysis.py
some EXTRA slots run empty now due to source/dest being the same
register (s:RA;d:RA)
openpower/isatables/LDSTRM-2P-2S1D.csv diff | blob | history
src/openpower/decoder/power_insn.py diff | blob | history
src/openpower/sv/sv_analysis.py diff | blob | history