gen/fhdl: add Display for debug in simulation
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 29 Apr 2016 21:03:43 +0000 (23:03 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 29 Apr 2016 21:03:43 +0000 (23:03 +0200)
commit69f003531531900f78e0c19dd9d933d0903ed38f
tree2687c454a62f5fc6dd2cdff55604cdc24b4c7c6b
parente79b2e3fefd9cf6ed5d3e671fbb50c989266afa4
gen/fhdl: add Display for debug in simulation
litex/gen/fhdl/structure.py
litex/gen/fhdl/verilog.py