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write_verilog: write RTLIL::Sa aka - as Verilog ?.
authorwhitequark <whitequark@whitequark.org>
Tue, 9 Jul 2019 18:30:24 +0000 (18:30 +0000)
committerwhitequark <whitequark@whitequark.org>
Tue, 9 Jul 2019 18:35:49 +0000 (18:35 +0000)
commit6a29e1f5b7e8ac36fcf8c5f00c509ebeaa5257e5
tree93563c725c5c63fcf1298b332ed8df8c95057288tree
parente95ce1f7af269447943cf1798c03b02a0c5aa1a2commit | diff
write_verilog: write RTLIL::Sa aka - as Verilog ?.

Currently, the only ways (determined by grepping for regex \bSa\b) to
end up with RTLIL::Sa in a netlist is by reading a Verilog constant
with ? in it as a part of case, or by running certain FSM passes.
Both of these cases should be round-tripped back to ? in Verilog.
backends/verilog/verilog_backend.cc diff | blob | history