Special abc9_clock wire to contain only clock signal
authorEddie Hung <eddie@fpgeh.com>
Mon, 25 Nov 2019 20:36:13 +0000 (12:36 -0800)
committerEddie Hung <eddie@fpgeh.com>
Mon, 25 Nov 2019 20:36:13 +0000 (12:36 -0800)
commit6a2eb5d8f9286b9574647c03e2bdc8b63fccbe4d
treee54a34ddf738604ee89a7e836ae1f75ded00ac7a
parent180cb3939546f68eca878a8427a043eb1169094c
Special abc9_clock wire to contain only clock signal
techlibs/xilinx/abc9_map.v