trellis, versa_ecp5: optional '-nowidelut' flag for yosys synth_ecp5
authorGabriel L. Somlo <gsomlo@gmail.com>
Thu, 8 Aug 2019 22:55:14 +0000 (18:55 -0400)
committerGabriel Somlo <gsomlo@gmail.com>
Sun, 6 Oct 2019 12:37:43 +0000 (08:37 -0400)
commit6aa76b1df8f17f8669eff3384bcedbeaf1eb87ed
tree56037bf045e9d0c968a1827c79f2bfefe4580b56
parentab4a5d1dc15a840288f39f1c621411cff13742af
trellis, versa_ecp5: optional '-nowidelut' flag for yosys synth_ecp5

Passing '-nowidelut' to yosys' synth_ecp5 command improves area utilization
to the point where a (linux variant) rocket-chip based design will fit on a
versa_ecp5 board. Usually '-nowidelut' incurs a timing penalty, but that is
then mitigated by using DSP inference (enabled by default from yosys commit
8474c5b3).

Off by default, this flag can be enabled by adding '--yosys-nowidelut=True'
to the litex/boards/targets/versa_ecp5.py command line.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
litex/boards/targets/versa_ecp5.py
litex/build/lattice/trellis.py