trellis, versa_ecp5: optional '-nowidelut' flag for yosys synth_ecp5
Passing '-nowidelut' to yosys' synth_ecp5 command improves area utilization
to the point where a (linux variant) rocket-chip based design will fit on a
versa_ecp5 board. Usually '-nowidelut' incurs a timing penalty, but that is
then mitigated by using DSP inference (enabled by default from yosys commit
8474c5b3).
Off by default, this flag can be enabled by adding '--yosys-nowidelut=True'
to the litex/boards/targets/versa_ecp5.py command line.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>