verilog: improve specify support when not in -specify mode
authorEddie Hung <eddie@fpgeh.com>
Thu, 13 Feb 2020 21:27:15 +0000 (13:27 -0800)
committerEddie Hung <eddie@fpgeh.com>
Thu, 13 Feb 2020 21:27:15 +0000 (13:27 -0800)
commit6b58c1820c7bbacb4730af40e10592823b0eb15c
treef878ff9902af732ca253999dcd596f6f987cc336
parent2e51dc1856aae456e15cafd484997bfbd102175e
verilog: improve specify support when not in -specify mode
frontends/verilog/verilog_parser.y
tests/various/specify.v
tests/various/specify.ys