projects / yosys.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 3931b3a) | patch
verilog: fix multiple AST_PREFIX scope resolution issues
authorZachary Snow <zach@zachjs.com>
Tue, 3 Aug 2021 00:42:34 +0000 (18:42 -0600)
committerZachary Snow <zachary.j.snow@gmail.com>
Tue, 21 Sep 2021 16:10:59 +0000 (12:10 -0400)
commit6b7267b849abf7688938e5e53ae7017e8588ff18
tree8a357899c2f0f2d00930f34fc83bbab63ab35528tree
parent3931b3a03f65965daca20b1228d8882192e74650commit | diff
verilog: fix multiple AST_PREFIX scope resolution issues

- Root AST_PREFIX nodes are now subject to genblk expansion to allow
  them to refer to a locally-visible generate block
- Part selects on AST_PREFIX member leafs can now refer to generate
  block items (previously would not resolve and raise an error)
- Add source location information to AST_PREFIX nodes
frontends/ast/simplify.cc diff | blob | history
frontends/verilog/verilog_parser.y diff | blob | history
tests/verilog/prefix.sv [new file with mode: 0644] blob
tests/verilog/prefix.ys [new file with mode: 0644] blob