Fix up a few statistics problems.
authorSteve Reinhardt <stever@eecs.umich.edu>
Sat, 30 Jun 2007 20:34:16 +0000 (13:34 -0700)
committerSteve Reinhardt <stever@eecs.umich.edu>
Sat, 30 Jun 2007 20:34:16 +0000 (13:34 -0700)
commit6babda7123be5e69db137e77589d88c768c19345
tree6317fb3559996a36602e3d66b5e0b5ea63a2a5f8
parent6ab53415efe3e06c06589a8a6ef38185ff6f94b7
Fix up a few statistics problems.
Stats pretty much line up with old code, except:
- bug in old code included L1 latency in L2 miss time, making it too high
- UniCoherence did cache-to-cache transfers even from non-owner caches,
so occasionally the icache would get a block from the dcache not the L2
- L2 can now receive ReadExReq from L1 since L1s have coherence

--HG--
extra : convert_revision : 5052c1a1767b5a662f30a88f16012165a73b791c
src/mem/cache/base_cache.cc
src/mem/cache/base_cache.hh
src/mem/cache/cache_impl.hh
src/mem/cache/miss/mshr.cc
src/mem/cache/miss/mshr.hh
src/mem/cache/miss/mshr_queue.cc
src/mem/cache/miss/mshr_queue.hh
src/mem/tport.hh