Don't blow up constants unneccessarily in Verilog frontend
authorClifford Wolf <clifford@clifford.at>
Mon, 24 Feb 2014 11:41:25 +0000 (12:41 +0100)
committerClifford Wolf <clifford@clifford.at>
Mon, 24 Feb 2014 11:41:25 +0000 (12:41 +0100)
commit6bc94b7eb2ecc7c2836c2fc10029542ce92eae11
tree7c6897cdcfe8e766d3b5ef5bcfd0f16beec00240
parentdab1612f81212d1bc1c07ee77b265167861ec883
Don't blow up constants unneccessarily in Verilog frontend
frontends/ast/genrtlil.cc