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(parent: 90bded1) | patch
radeonsi: fix typo in DPBB register field
authorPierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Fri, 2 Aug 2019 10:05:15 +0000 (12:05 +0200)
committerMarek Olšák <marek.olsak@amd.com>
Wed, 7 Aug 2019 22:45:20 +0000 (18:45 -0400)
commit6bda9ca062748f61ff0ab57e4d68aae5cf98308a
treee81efd8ca6edd1f8243e4f290e81f5d96f92517etree
parent90bded140ecc41a6a100b477006c040de8fb2e65commit | diff
radeonsi: fix typo in DPBB register field

Also only set FLUSH_ON_BINNING_TRANSITION for GPU families that needs it (matches
what si_emit_dpbb_disable is doing).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
src/gallium/drivers/radeonsi/si_state_binning.c diff | blob | history