x86: Mark translation as delayed in case of a hw page table walk
authorGabor Dozsa <gabor.dozsa@arm.com>
Tue, 30 Apr 2019 09:20:40 +0000 (10:20 +0100)
committerGabor Dozsa <gabor.dozsa@arm.com>
Tue, 7 May 2019 09:42:45 +0000 (09:42 +0000)
commit6bf8508fdcc0909103090e2747584ac4596a204d
treeef001417274d39e4bb8faf7b15a887d7d92242d4
parent7a00e9d186f4b1ad463b9e0adf46cbfbe9f0d87b
x86: Mark translation as delayed in case of a hw page table walk

This information is used by the LSQ in the O3 cpu (since commit
"51becd2... cpu-o3: O3 LSQ Generalisation")

Change-Id: I35fe7e2f8428641d863af0e79e28b0b259fb0b00
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18508
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/x86/tlb.cc