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Re: [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
authorJacob Lifshay <programmerjake@gmail.com>
Wed, 13 May 2020 19:02:41 +0000 (12:02 -0700)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Wed, 13 May 2020 19:02:55 +0000 (20:02 +0100)
commit6c18a4277a6283dfa6f0243b918d362c43468d56
treec45adfab484bc2834b0482b47e2076de628c6399tree
parent024cfe17e875ace857cc98bbea1839fa5976de7ccommit | diff
Re: [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
c1/6c8523131289eec611e84fb32b6cc39b97caa2 [new file with mode: 0644] blob
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