intel/compiler: fix node interference of simd16 instructions
authorIago Toral Quiroga <itoral@igalia.com>
Wed, 17 Oct 2018 10:05:42 +0000 (12:05 +0200)
committerIago Toral Quiroga <itoral@igalia.com>
Fri, 9 Nov 2018 07:22:08 +0000 (08:22 +0100)
commit6c418dfa42bfe38dc4525c9d2df12d0798ee64d3
treeb19384d7cc6ae903fc4012c054a48c3f5fb26f23
parenta3c898dc97ec5f0e0b93b2ee180bdf8ca3bab14c
intel/compiler: fix node interference of simd16 instructions

SIMD16 instructions need to have additional interferences to prevent
source / destination hazards when the source and destination registers
are off by one register.

While we already have code to handle this, it was only running for SIMD16
dispatches, however, we can have SIDM16 instructions in a SIMD8 dispatch.
An example of this are pull constant loads since commit b56fa830c6095,
but there are more cases.

This fixes a number of CTS test failures found in work-in-progress
tests that were hitting this situation for 16-wide pull constants
in a SIMD8 program.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
src/intel/compiler/brw_fs_reg_allocate.cpp