mem: Align downstream cache packet creation in atomic and timing
authorAndreas Hansson <andreas.hansson@arm.com>
Thu, 21 Apr 2016 08:48:06 +0000 (04:48 -0400)
committerAndreas Hansson <andreas.hansson@arm.com>
Thu, 21 Apr 2016 08:48:06 +0000 (04:48 -0400)
commit6c92ee49f1125559ffc7c20cfe96306b9c4de017
tree2c74e0d43480d725ed436145a5c5ce93b105d824
parent53d735b17ee1a3bd27173138ed1937a45f20bc12
mem: Align downstream cache packet creation in atomic and timing

This patch makes the control flow more uniform in atomic and timing,
ultimately making the code easier to understand.
src/mem/cache/cache.cc
src/mem/cache/cache.hh