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(parent: 6744670) | patch
SOC memory wishbone should clear ACK regardless of STB
authorAnton Blanchard <anton@linux.ibm.com>
Wed, 11 Sep 2019 07:21:52 +0000 (17:21 +1000)
committerAnton Blanchard <anton@ozlabs.org>
Thu, 12 Sep 2019 05:57:00 +0000 (15:57 +1000)
commit6cbf45638882cc37bba2429dccfbcd473bdc8147
tree6d54d3588f4156b606fa887780107a33709e38f2tree
parent67446709caea183942320140d0cce0dc8c563fafcommit | diff
SOC memory wishbone should clear ACK regardless of STB

The memory wishbone doesn't clear ACK and move the state machine on
until STB is de-asserted. This seems like it isn't compliant with
the spec and results in a maximum throughput of 1 transfer every
3 cycles.

Fixing this improves the situation to one transfer every 2 cycles.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
fpga/mw_soc_memory.vhdl diff | blob | history