Merge pull request #679 from udif/pr_syntax_error
authorClifford Wolf <clifford@clifford.at>
Thu, 25 Oct 2018 11:18:59 +0000 (13:18 +0200)
committerGitHub <noreply@github.com>
Thu, 25 Oct 2018 11:18:59 +0000 (13:18 +0200)
commit6cd5b8b76ba9f9df04571defa33fc862aec87924
tree16cdd1c333ac25625713c0941ddc3fceb0354efa
parent7703be045a0a46ed70ec19b5db731e33fa56cef5
parent536ae16c3abcf3fef1dd14df8733bf51fa1bce1a
Merge pull request #679 from udif/pr_syntax_error

More meaningful SystemVerilog/Verilog parser error messages