MEM: Fix residual bus ports and make them master/slave
authorAndreas Hansson <andreas.hansson@arm.com>
Tue, 14 Feb 2012 19:15:30 +0000 (14:15 -0500)
committerAndreas Hansson <andreas.hansson@arm.com>
Tue, 14 Feb 2012 19:15:30 +0000 (14:15 -0500)
commit6cf9f182f678e4ddf2a2b98a5093a7418353217c
tree9de2665814818b7ce04cf7b2c85cc907b71a3581
parentac91f90145f824b202d79a9e275fc5cee1071159
MEM: Fix residual bus ports and make them master/slave

This patch cleans up a number of remaining uses of bus.port which
is now split into bus.master and bus.slave. The only non-trivial change
is the memtest where the level building now has to be aware of the role
of the ports used in the previous level.
configs/example/memtest.py
configs/splash2/cluster.py
configs/splash2/run.py
src/dev/arm/RealView.py
src/dev/mips/Malta.py
src/dev/sparc/T1000.py