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Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
authorStaf Verhaegen <staf@fibraservi.eu>
Wed, 20 May 2020 16:44:06 +0000 (18:44 +0200)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Wed, 20 May 2020 16:44:13 +0000 (17:44 +0100)
commit6d05b7a3f253cb2c71a4565877b19f7a4510ea14
treeaf4200d9db340cc683ccd98bbfcc2e766074b568tree
parent7d63b11647a94e6c09a41120d5b8708de1c4a053commit | diff
Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
b9/8be2490e3018ad12c487017ad4922a90e41587 [new file with mode: 0644] blob
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