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(parent: 5ac02ab) | patch
only add SVP64 bitreverse mode for LDs at the moment. ST would need 4 operands
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 23 Jun 2021 21:42:37 +0000 (22:42 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 23 Jun 2021 21:42:37 +0000 (22:42 +0100)
commit6d86b3df2af9ca2d1acdac155973d3582210d06d
tree5b8c14fc6ad7950b3d752104e5ed651fe6db493atree
parent5ac02abd7435659037b3f33928976de99c7c53c2commit | diff
only add SVP64 bitreverse mode for LDs at the moment. ST would need 4 operands
add RC to PowerDecoder
add create_decode_svp64
sort out Forms and Const names in enums
openpower/isatables/fields.text diff | blob | history
openpower/isatables/svldst_major.csv [new file with mode: 0644] blob
openpower/isatables/svldstmajor.csv [deleted file] blob | history
src/openpower/decoder/power_decoder.py diff | blob | history
src/openpower/decoder/power_decoder2.py diff | blob | history
src/openpower/decoder/power_enums.py diff | blob | history
src/openpower/decoder/power_fields.py diff | blob | history