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(parent: 2c1e150) | patch
Made changes recommended by Clifford Wolf ...
authorluke whittlesey <luke.whittlesey@gmail.com>
Sun, 10 May 2015 15:33:24 +0000 (11:33 -0400)
committerluke whittlesey <luke.whittlesey@gmail.com>
Sun, 10 May 2015 15:33:24 +0000 (11:33 -0400)
commit6de8fea2c77abb936ba2356bf5c1425a15f5edd7
treeca6e06d250560e918f669c7d566115ba0a5c31d9tree
parent2c1e15029786fe8a118343b7a81f681450a8ce93commit | diff
Made changes recommended by Clifford Wolf ...

Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used
dict<> instead of std::map, and used RTLIL::SigSpec instead of
std::vector.
backends/verilog/verilog_backend.cc diff | blob | history