arch-arm: GenericTimer arch regs, perms/trapping

arch-arm: GenericTimer arch regs, perms/trapping

This patch enhances the Generic Timer architected registers handling:

- Reordering of miscregs for easier switch/case ranges
- Implement _EL12 reg versions for E2H environments
- AArch32/64 EL0/EL1/EL2 arch compliant trapping for all registers
    + Rely on CNTKCTL and CNTHCTL access controls
- UNDEFINED behaviour from EL0(NS)
- EL1(S) timer traps to EL3 when SCR.ST == 0

Change-Id: I4f018e103cf8f7323060516121838f90278b1c3e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25307
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>