projects / nmigen.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 5361b4c) | patch
back.verilog: do not rename internal signals.
authorwhitequark <whitequark@whitequark.org>
Sat, 22 Dec 2018 00:53:40 +0000 (00:53 +0000)
committerwhitequark <whitequark@whitequark.org>
Sat, 22 Dec 2018 00:53:40 +0000 (00:53 +0000)
commit6ee80408bbb5449d4a176c187ab895d4e4f5e054
treec1029d491da24921e10ba4fff6b0688eea35473btree
parent5361b4c22b0f71d461dd195b347afb69e9154cedcommit | diff
back.verilog: do not rename internal signals.

_0_ is not really any better than \$13, and the latter at least has
continuity between nMigen, RTLIL and Verilog.
nmigen/back/verilog.py diff | blob | history