fhdl/verilog: create clock domains in deterministic order
authorSebastien Bourdeauducq <sb@m-labs.hk>
Thu, 5 Nov 2015 07:06:33 +0000 (15:06 +0800)
committerSebastien Bourdeauducq <sb@m-labs.hk>
Thu, 5 Nov 2015 07:06:33 +0000 (15:06 +0800)
commit6f5bf0292e2886f00ccf6c09a64a1b198ed33383
treecc7bcc169d301bd809d37f3aed591abc0a010ed6
parent180ba95dd417407dd1ec4647af28fdda71ba77f2
fhdl/verilog: create clock domains in deterministic order
migen/fhdl/verilog.py