fhdl/verilog: tristate outputs are always wire
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Wed, 6 Mar 2013 10:30:52 +0000 (11:30 +0100)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Wed, 6 Mar 2013 10:30:52 +0000 (11:30 +0100)
commit6fa30053bf1b247007426e61bee1a286f0226390
tree497021ab97801daf6e86ceeeed3d29ab40962f4d
parent9b4ca987e04591d5e865fe0797566b4d114f2134
fhdl/verilog: tristate outputs are always wire
migen/fhdl/verilog.py