litedram: Add simulation support
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Fri, 22 May 2020 08:43:50 +0000 (18:43 +1000)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Fri, 5 Jun 2020 00:24:47 +0000 (10:24 +1000)
commit6fe077910bff64841522230150a379dd664b5c8e
tree6dc0e7ba51c3a8af04d3581aa10fa96e8958c487
parent42e138e539c0e254745611600206b08989ed6aa7
litedram: Add simulation support

This adds a simulated litedram model along with the necessary
Makefile gunk to verilate it and wrap it for use by ghdl.

The core_dram_tb test bench is a variant of core_tb with
LiteDRAM simulated. It's not built by default, an explicit

make core_dram_tb

is necessary as to not require verilator to be installed for
the normal build process (also it's slow'ish).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
26 files changed:
Makefile
core_dram_tb.vhdl [new file with mode: 0644]
litedram/extras/fusesoc-add-files.py
litedram/extras/sim_dram_verilate.mk [new file with mode: 0644]
litedram/extras/sim_litedram.vhdl [new file with mode: 0644]
litedram/extras/sim_litedram_c.cpp [new file with mode: 0644]
litedram/extras/wrapper-mw-init.vhdl [new file with mode: 0644]
litedram/extras/wrapper-self-init.vhdl [new file with mode: 0644]
litedram/gen-src/generate.py
litedram/gen-src/sdram_init/Makefile
litedram/gen-src/sdram_init/include/system.h
litedram/gen-src/sim.yml [new file with mode: 0644]
litedram/gen-src/wrapper-mw-init.vhdl [deleted file]
litedram/gen-src/wrapper-self-init.vhdl [deleted file]
litedram/generated/arty/init-cpu.txt [new file with mode: 0644]
litedram/generated/arty/litedram-wrapper.vhdl [deleted file]
litedram/generated/arty/litedram_core.init
litedram/generated/arty/litedram_core.v
litedram/generated/nexys-video/init-cpu.txt [new file with mode: 0644]
litedram/generated/nexys-video/litedram-wrapper.vhdl [deleted file]
litedram/generated/nexys-video/litedram_core.init
litedram/generated/nexys-video/litedram_core.v
litedram/generated/sim/init-cpu.txt [new file with mode: 0644]
litedram/generated/sim/litedram-initmem.vhdl [new file with mode: 0644]
litedram/generated/sim/litedram_core.init [new file with mode: 0644]
litedram/generated/sim/litedram_core.v [new file with mode: 0644]