vendor.xilinx_{7series,ultrascale}: don't use `write_verilog -decimal`.
authorwhitequark <whitequark@whitequark.org>
Thu, 21 May 2020 08:57:30 +0000 (08:57 +0000)
committerwhitequark <whitequark@whitequark.org>
Thu, 21 May 2020 08:57:43 +0000 (08:57 +0000)
commit702e41ba3c2cc7561efb3e40d01732bd9fec89fc
treec4e3dd6c9a59bd7c9b98cc4ea5abab4b24113676
parent3420b683a30f99c85a26b8e849f85622b1df35d7
vendor.xilinx_{7series,ultrascale}: don't use `write_verilog -decimal`.

In commit 892cff05, `-decimal` was used when writing Verilog for
Vivado targets because it treats (* keep=32'd1 *) and (* keep=1 *)
differently in violation of Verilog LRM. However, it is possible
to avoid that workaround by using (* keep="TRUE" *). Do that,
and remove `-decimal` to avoid special-casing 32-bit constants.

Refs #373.
nmigen/vendor/xilinx_7series.py
nmigen/vendor/xilinx_ultrascale.py