add core instruction-issue PriorityPickers
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 9 Nov 2021 17:49:30 +0000 (17:49 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 9 Nov 2021 17:49:30 +0000 (17:49 +0000)
commit7036fbf292ed8a5bc8393c3c95e15a28870ee325
tree4c6a7707759bbd96df0d97867e974e9663690e69
parentf8f7b525146f1100c48a4d74b79c50811638690e
add core instruction-issue PriorityPickers

this got more complicated than expected.  it should have been dead easy:
* identify each type of ALU (Logical, Shift, Mul)
* create a list per type of ALU of all Function Units providing that Function
* create a PriorityPicker for each type of ALU
* pick one
* shove that into the "issue" of the picked Function Unit.

where that went wrong was nothing to do with issue, it was to do with the
selection of the register files.

a return result from connect_instruction is a dictionary of "enabled"
bits, one per FU, giving permission for that FU to perform read/write
access to regfile ports.

however with the fu_bitdict changing from "continuously-enabled" over
to "single-pulse indicating issue", the read/write ports were no longer
requested.

to fix this, an *additional* dictionary was created: fu_selected, which
has the OR of the FU issue *and* the FU "busy" signal, which will be
HI for the whole time that the FU is active (even including the first
issue cycle: normally busy_o only goes active one cycle *after* issue
is blipped)

thus in theory, although in practice it will not happen, the read/write
ports could be requested immediately the instruction is issued.
src/soc/simple/core.py