add misaligned mem test
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 30 Dec 2022 13:20:56 +0000 (13:20 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 30 Dec 2022 13:20:56 +0000 (13:20 +0000)
commit70498a68baab54982ffaf2300f51d77d21c1b252
tree693be208c8abd7a7fae4a1142b8d261661739d6e
parent470be69f873dc7b0c5c07fb892367e08a78c7bbd
add misaligned mem test
src/openpower/decoder/isa/test_mem.py