Merge pull request #988 from YosysHQ/clifford/fix987
authorClifford Wolf <clifford@clifford.at>
Sat, 4 May 2019 19:58:25 +0000 (21:58 +0200)
committerGitHub <noreply@github.com>
Sat, 4 May 2019 19:58:25 +0000 (21:58 +0200)
commit70d0f389ad6e7e0ad762b62d3a626a4db5b23827
tree285b758efa19342a8e136772190d55672329cba2
parenta01386c0e45b4eee5295db440740a1ab271396fe
parent9804c86e87ec83edd29d224f01311b6ae1d41181
Merge pull request #988 from YosysHQ/clifford/fix987

Add approximate support for SV "var" keyword
frontends/verilog/verilog_lexer.l
frontends/verilog/verilog_parser.y