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(parent: 8548fe1) | patch
aco: reorder VMEM operands in ACO IR
authorDaniel Schürmann <daniel@schuermann.dev>
Thu, 16 Jan 2020 15:54:35 +0000 (16:54 +0100)
committerMarge Bot <eric+marge@anholt.net>
Wed, 29 Jan 2020 18:45:23 +0000 (18:45 +0000)
commit71440ba0f5512fe455be66ca48b253ecc37478a9
treeae9619e671d1e87a3bbef4d002d7bcc75b32fee5tree
parent8548fe19f03ecaee711ed9041be3dc05c7c22e56commit | diff
aco: reorder VMEM operands in ACO IR

For all VMEM instructions, the resource constant is now
in operands[0]. For MIMG instructions, the sampler shares
operands[1] with write data in case this instruction writes memory.
Moving the VADDR to be the last operand for MIMG is the first step to
support Navi NSA encoding.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3602>
src/amd/compiler/aco_assembler.cpp diff | blob | history
src/amd/compiler/aco_builder_h.py diff | blob | history
src/amd/compiler/aco_insert_NOPs.cpp diff | blob | history
src/amd/compiler/aco_insert_waitcnt.cpp diff | blob | history
src/amd/compiler/aco_instruction_selection.cpp diff | blob | history
src/amd/compiler/aco_ir.h diff | blob | history
src/amd/compiler/aco_optimizer.cpp diff | blob | history
src/amd/compiler/aco_register_allocation.cpp diff | blob | history
src/amd/compiler/aco_scheduler.cpp diff | blob | history
src/amd/compiler/aco_spill.cpp diff | blob | history
src/amd/compiler/aco_validate.cpp diff | blob | history