arch-riscv: Move parts of mem insts out of ISA
authorAlec Roelke <ar4jc@virginia.edu>
Tue, 7 Nov 2017 20:19:56 +0000 (15:19 -0500)
committerAlec Roelke <ar4jc@virginia.edu>
Wed, 29 Nov 2017 00:58:23 +0000 (00:58 +0000)
commit719ddf73afa62735881ac68acf681abe1bf3bd17
tree71ba0ac50a066504c9df48cde18ba65f2da05689
parent19ad3c4ae46426e988602d870dc2c27fee1154f1
arch-riscv: Move parts of mem insts out of ISA

This patch moves static portions of the memory instructions out of the
ISA generated code and puts them into arch/riscv/insts.  It also
simplifies the definitions of load and store instructions by giving
them a common base class.

Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803
Reviewed-on: https://gem5-review.googlesource.com/6024
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
src/arch/riscv/insts/SConscript
src/arch/riscv/insts/bitfields.hh
src/arch/riscv/insts/mem.cc [new file with mode: 0644]
src/arch/riscv/insts/mem.hh [new file with mode: 0644]
src/arch/riscv/isa/decoder.isa
src/arch/riscv/isa/formats/mem.isa
src/arch/riscv/isa/includes.isa