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(parent: 9b239f4) | patch
test.compat: reenable tests converting to Verilog.
authorwhitequark <cz@m-labs.hk>
Sat, 26 Jan 2019 15:29:09 +0000 (15:29 +0000)
committerwhitequark <cz@m-labs.hk>
Sat, 26 Jan 2019 15:29:09 +0000 (15:29 +0000)
commit71a70da437332fa0a26a6d7d05cfa7577d7e6b5f
treedf0756986df99ba5dcf31c307b40792679cc74cctree
parent9b239f41455805e4057f0779d562901a63ff7865commit | diff
test.compat: reenable tests converting to Verilog.
nmigen/compat/fhdl/verilog.py diff | blob | history
nmigen/test/compat/support.py diff | blob | history