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(parent: 9032665) | patch
soc/interconnect/stream: use valid/ready/last signals instead of stb/ack/eop (similar...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 16 Mar 2016 19:06:05 +0000 (20:06 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 16 Mar 2016 19:13:47 +0000 (20:13 +0100)
commit71a719be44639e43b26c9225479ed739795c642c
tree14f5e00c619eff58fac77495e1a059a106146850tree
parent90326657507777b2aa0b49d6b9e3b686262c7799commit | diff
soc/interconnect/stream: use valid/ready/last signals instead of stb/ack/eop (similar to AXI)
litex/soc/cores/uart/core.py diff | blob | history
litex/soc/interconnect/dma_lasmi.py diff | blob | history
litex/soc/interconnect/stream.py diff | blob | history
litex/soc/interconnect/stream_packet.py diff | blob | history
litex/soc/interconnect/stream_sim.py diff | blob | history
litex/soc/interconnect/wishbonebridge.py diff | blob | history